Memories typically include an array of memory cells arranged in rows and columns. Memory cells of each row are accessed by activating a corresponding access line often referred to as a word line. The word line may be activated by a word line driver responsive to decoding a corresponding row address with a row address decoder.
Word line drivers typically comprise a p-channel field effect transistor (pFET) and an n-channel field effect transistor (nFET) coupled together at their respective drains and gates, forming a complementary FET output stage coupled to the word line at the drains of the transistors. The source of the pFET can be configured to receive, for example, a phase signal (e.g., from a phase decoder). Meanwhile, the source of the nFET can be configured to receive, for example, a deactivated word line voltage (e.g., VNEGWL). Assuming a sufficiently high voltage phase signal (e.g., VCCP, which may be a pumped supply voltage) is provided as the phase signal to the source of its word line driver, a word line may be activated by providing a sufficiently low voltage (e.g., ground) to the gate of the pFET to turn on the pFET and pull the word line up to ˜VCCP. To deactivate the word line (e.g., to close the row), as is typically desired after a row of memory cells has been accessed (e.g., refreshed), a sufficiently high voltage (e.g., VCCP) is provided to the gate of the nFET to quickly turn on the nFET and pull the word line down to ˜VNEGWL.
A performance issue associated with the use of such a word line driver is gate-induced diode leakage (GIDL) current. GIDL currents may arise when the pFET of a word line driver experiences a relatively significant gate-to-source voltage such that current leaks from the n-well to the source of the pFET when the transistor is operating in an “off” state. Since the gates of the pFET and nFET transistors are coupled together in such a word line driver, this can occur when VCCP is being provided to the gate of the pFET (and thus also to the gate of the nFET) and ground is provided as the voltage for the phase signal, such as when the memory is in a standby mode. During the standby mode, the memory cells are not accessed and the operational state of the memory is such that power consumption is reduced. Because numerous word line drivers may be used simultaneously in a memory system, GIDL current can result in substantial unwanted power consumption, even during a standby mode for the memory.